Digital equipment interface unit

ABSTRACT

A programmable interface unit for use with automatic digital test equipment having a plurality of generator/comparator units which couple stimuli signals from a plurality of shift registers to a unit under test and evaluate output signals produced by the unit under test in response to the stimuli signals by comparing the output signals to programmable reference levels. Each terminal of the interface unit coupled between the generator/comparators and the unit under test may be employed alternately by appropriate programming to function as either a stimuli output to the unit under test or as an input to a comparator of an output signal produced by the unit under test.

United States Patent Burdette, Jr. et al.

1111 3,739,349 1 June 12, 1973 DIGITAL EQUIPMENT INTERFACE UNIT3,505,598 4/1970 Merrill 324/77 75 Inventors: willilzl n11. Big-ra tan,g 3:22:33; 151333 .1: I:

Dav av ,Jr., earwater, both of Primary Examiner-Paul J. Henon [73]Assignees Sperry Rand Corporation, New Assistant Examiner-Mark EdwardNusbaum York, NY. Attorney-S. C. Yeaton [21] Appl. No.: 146,263 Aprogrammable interface unit for use with automatic di ital test equiment havin a pluralit of eneratorl- 3 P g 5 [52] U 8 CL 340". 5 324,73comparator units wh1ch couple stlmuh signals from a [51 i 31/00plurality of shift registers to a unit under test and evalu- 58] Field235/157, ate output signals produced by the unit under test in re- 1 5 R73 i sponse to the stimuli signals by comparing the output signals toprogrammable reference levels. Each termi- [56] References Cited nal ofthe interface unit coupled between the generator/comparators and theunit under test may be em- UNITED STATES PATENTS ployed alternately byappropriate programming to 3,602,309 1971 a el al 324/73 R function aseither a stimuli output to the unit under test wi zis or as an input toa comparator of an output signal pro- 3:478:286 11/1969 Dervan III...11:: 340/1725 duced by under test 3,576,541 4/1971 Kwan et al 340/1725 9Claims, 2 Drawing Figures 1 f 1 1 r 1 1 1 1 1 1 1 1 c w 1 GT3; o ma 2?7A 12 T 11 1mm 1 1111 1111a 34 D D 17 M ?I mm o-- 11K in 23 28 32 i%tS"5 1, W. 2::? pmiw :33 I) 11:0 b VT j 111:

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Patented June 12, 1973 3,739,349

2 Sheets-Sheet 1 REF REF V V+ V- VSR SIGNAL I on CLEAR o cue l2 DATA ooCLOCK c CLK EVALUATE CLOCK o EVCLK COMPARATOR 16 T ENABLE c COMP EN b 26[11 ADDRESS ENABLE SELECT A 12 GIROUPHCENABLE SELECTO oATAo REGISTER i li C CLR 0 CLK 8-BIT 4 an SELECTl SHIFT LATCH DATA 0 c REGISTER DECODERl, l, l

CLR 0 cu I14 B-BIT 551.2012 SH'FT DATA 0 w REGISTER CLR 0 CLK f15 e-anSELECT3 SHIFT -o DATA 3 REGISTER cm 0 CLK CLR INVENTORS WILL/AM M,BURDETTE DAV/D C DAV/S 1 DIGITAL EQUIPMENT INTERFACE UNIT BACKGROUND OFTHE INVENTION 1. Field of the Invention This invention pertains to aclass of equipment used in testing digital electronic apparatus andspecifically to automatic equipments which perform a plurality of teststhat heretofore required many different interface elements between thetest equipment and the apparatus under test.

2. Description of the Prior Art In the prior art, a Program Storage andRouting (PSR) card is utilized to interface between a specific unit of asystem under test and the automatic test equipment. The output lines onthe PSR card couple programmable power supplies to the unit from thetest equipment. These lines include the required voltage levels andtheir respective returns. To standardize the design of the cards,certain output terminals on each card are reserved for specific voltagelevels. Other signals coupled between the unit under test and the testequipment include digital ones and zeroes referred to as stimulisignals, clear pulses, clock frequency signals and output signalsgenerated by the unit under test in response to the stimuli signals. Aparticular PSR card could be used for one or possibly two tests becausethe terminals on each unit require the coupling of different types ofsignals to and from the test equipment. Therefore, each PSR card isdesigned to accommodate the performance of particular tests of specificunits. As the number of different units and the number of differenttests to be performed increases, the number of PSR cards required alsoincreases. It can be appreciated that the setup time for testing isincreased, thereby decreasing the efficiency of the automatic testequipment. Further, storage capacity is necessitated in order toaccommodate the multiplicity of PSR cards.

SUMMARY OF THE INVENTION The present invention is an interface unitwhich couples a plurality of different signals on the same outputterminals between automatic test equipment and units to be tested. Thisinterface unit includes a decoder which processes received stimuli datainputs and applies the decoded stimuli outputs through parallelconnected shift registers to a stimuli latch circuit. Programmed bitinputs are applied to a plurality of bit latch circuits that providecontrol outputs. Generator/- comparator circuits each of which includesa transistorized switch and a pair of integrated circuit comparatorsreceives input signals from the stimuli latch circuit and controlsignals from the bit latch circuits. The output of the transistorizedswitch and the inputs to the pair of integrated circuit comparators ineach generator/comparator are connected in common with one outputterminal of the interface unit. Thus, as a function of time, an outputterminal of the interface assembly may couple a stimuli signal to theunit under test and subsequently couple an output signal from the unitunder test into the integrated circuit comparators. The stimuli signalsmay be digital ones or zeroes, clear pulses or clock frequency signals.Therefore, this device provides a single unit that obviates the need fora multiplicity of interface or Program, Storage, Routing (PSR) cardsthereby enabling an increase in testing efficiency while reducingtesting complexity and cost without any degradation in the accuracy ofthe test measurements obtained.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1a and FIG. 1b combine to form ablock diagram of the digital interface device including a schematicdiagram of two generator/comparator circuits.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the FIGURE, aninterface device 10 includes a decoder 11 which may be an integratedcircuit element that converts a digital number appearing on the inputsDATA Q0. DATA Q1. DATA 0 and DATA 0; into a pulse output on one of thelines SELECT 0, SELECT 1, SELECT 2, or SELECT 3. The decoder 11 iscoupled via the select lines to a plurality of eight bit shift registersl2, l3, l4 and 15. Each of the shift registers has input terminals whichreceive DATA, CLOCK and CLEAR inputs, respectively. In addition to itscorresponding select input, the output terminal of each shift register12-15 are connected to respective input terminals on a four bit latchcircuit 16 which is a delay circuit responsive to external gating.Output stimuli signals from that latch circuit 16 designated S arecoupled into corresponding comparator/generator circuits 17, 20, 21 and22 which are identical schematically to 17 and 20 shown within thedashed lines in the figure. A further line designated SELECT A isconnected to input gates 27 and 30. The signal on the SE L ECT A line isderived from the inputs ADDRESS ENABLE and GROUP ENABLE gated into thedecoder 11 by a gate 26. Each stimuli signal, S is applied to the baseof a switching transistor, for example, transistor 31. The collector ofthe transistor 31 is coupled through a collector resistor 32 to a supplyvoltage Vs and the emitter of the transistor 31 is connected directly toa return for the supply voltage designated Vsr. An output stimulisignal, S,,, is obtained from the junction of the collector resistor 32and the collector of transistor 31. The output stimuli signal is appliedto an output terminal, l,,, which is connected to a terminal on a unitunder test as indicated by the leader in the figure.

Each of the comparator/ generators also receives control inputs C and Cfrom either of the four bit latch circuits 23 or 24. These controlinputs enable the operation of one of the two comparators in eachcomparator/generator, for example, comparator 33 or 34 incomparator/generator 17. The latch circuits 23 and 24 are similar to the4 bit latch circuit 16 in that they are delay circuits responsive toexternal gating. The state, 0 or 1, of the programmable bits 1 through 8determine the state of the respective control inputs C and C, that areapplied to the comparators through the latch circuits 23 and 24.

Programmable reference voltages REF 1 and REF 0 are applied to referenceinput terminals on the respective comparators. REF 1 is the minimumallowable level for a one or high level and REF 0 is the maximumallowable level for a zero or low level. These levels may also beselected by appropriate programming. Thus, when C enables comparator 33,an output voltage re ceived from the unit under test is compared toREF 1. Alternatively, when C enables comparator 34, the output voltagereceived from the unit under test is compared to REF 0. As a result ofthis comparison test, either comparator 33 or comparator 34 will providean output signal TRO indicative of the result of the test. A 4 bit shiflregister 25 has one input terminal connected to a corresponding outputterminal on each of the comparator/generators 17, 20, 21 and 22. Eachcomparator produces indicator output signals which are applied to thecorresponding input terminal on the shift register 25. The indicatorsignals are processed through the shift register 25 in response toappropriate signals on the COMP EN and EV CLK lines thereby producing aGO/NO 60 signal output from the interface unit for each input receivedfrom the comparators.

In operation, consider a test to be performed on two different units. Onthe first unit under test, a stimuli signal S, is required from theoutput terminal 1,, and the unit under test provides an output signal tothe interface device l As determined from the bit data inputs applied tothe interface divide l0, accordin to Table A, zeroes are required onABBRE ERABLE, GROUP ENABLE, DATA Q0. DATA 0.. DATA Q, and DATA Q, toobtain a zero on the which will enable its corresponding 8 bit shiftregister 12.

TABLE A Address Group Select Enable Enable Q, Q, Q, Q, 0 l 2 3 0 l X X XX l l 1 l l 0 X X X X l l l l l l X X X X l l l l 0 0 0 O 0 0 0 l l l 00 0 0 U l l 0 l l 0 0 0 0 l O l l 0 l 0 0 0 0 l l l l l 0 The stimulisignal required on I, for the test is serial data clocked into shiftregister 12 on its data input terminal, D. The data input may be aprogrammable eight bit data word stored in another shift register.

During loading of the shift register 12, the four bit latch circuit 16prevents the input from being transferred to the comparator/generator17. When both input terminals of the dual input gate 28 connected to thefour bit latch circuit 16 have zeroes applied, the outputs 5,, followthe inputs from their corresponding shift registers 12-15. Since oneinput terminal on the dual input gate 28 is connected to ground, italways has a zero a lied. Therefore, when a zero is applied to MNterminal, the data transferred to the comparator/generators will followthe state of the in ut data. Upon application of a one level to theSTGNAL 6 terminal, the transferred data will remain in the state of theinput data at the time the one level was applied irrespective of furtherchanges in the input data. This condition prevails until a zero isapplied to the CLEAR terminal of the four bit latch circuit 16, at whichtime all the input and output data lines are reset to zeroes.

Thus, prior to loading, a zero is applied to the CLEAR terminal of thefour bit latch circuit 16 which produces zeroes on the input and out utdata lines. Then a one level is applied to the TGT5AL 6N input whichwill maintain the output data lines at zeroes irrespective of furtherchanges on the data input lines. As a result, the stimuli signals whichare being stored in the shift register 12 are not transferred throughthe 4 bit dual latch circuit 16 to the unit under test. After thestimuli signals have been stored in the shift register 12,

6 the test is gerformed by applying a zero level to the input and aCLOCK signal which may be a programmable train of pulses to the CLOCKinput terminal. The stimuli signals, S are coupled into the base of thetransistor 31 and the inverter output stimuli signals, 8,, are obtainedfrom the collector of the transistor 31. By varying the amplitude of thesupply voltage Vs applied to the collector resistor 32, the level of theoutput stimuli signals 5,, can be controlled. The output stimulisignals, 8,, are applied to the unit under test through the interfaceoutput terminal 1,. In response to the applied stimuli signals, 5,, thefirst unit under test will produce an output signal on output terminalL. This output signal is coupled into the comparator/generator 20 andapplied to the inputs of comparators 38 and 37 one of which is enabledby control input C, or C,, respectively, as determined by the input bits1 through 4. The input S, from the unit under test is compared to REF 1in comparator 37 if C, is high or it is compared to REF 0 in comparator38 if C, is high. The test result of the comparison appears on TRl andis cou led into the 4 bit shift register 25 when the COM? EN input goesto a zero followed by a transition from a zero to a one on EV CLK. Eachoutput on lines TRO through TR3 is sequentially coupled into shiftregister 25. These outputs are shifted through shift register 25 and areproduced as GO/NO GO outputs by successive clock pulses. Therefore, ifthe output signal from the module under test is a one, it is compared toREF 1 in comparator 37 and if it is greater than REF 1, it will producea G0 output signal from the shift register 25 or if it is less than REF1, it will produce a N0 G0 output signal. Alternatively, if the outputsignal from the module under test is a zero, it is compared to REF 0 incomparator 38 and if it is less than REF 0, it will produce a G0 outputsignal from the shift register 25 or if it is greater than REF 0, itwill produce a NO/GO output signal.

Since the foregoing test can be interchanged betweengenerator/comparators 17 and 20 on a second unit under test, by simpleprogramming changes, the versatility of this device can be readilyappreciated. Further, because the output lines on the interface unit 10can be employed as either stimuli lines or as comparator lines forcoupling outputs from the unit under test to the dual input comparators17, 20, 21 and 22, it eliminates the multiplicity of interface cards orPSR cards required in previous test equipment interface units.

While the invention has been described in its preferred embodiment, itis to be understood that the words which have been used are words ofdescription rather than limitation and that changes may be made withinthe purview of the appended claims without departing from the true scopeand spirit of the invention in its broader aspects.

We claim:

1. An interface device for coupling between electronic test apparatusand equipment under test having a plurality of input/output terminals,each of said input- /output terminals to be used as either an outputterminal for applying stimuli signals to the equipment under test or asan input terminal for receiving signals produced by said equipment undertest, said interface device comprising:

a source of stimuli signals for simultaneously providing a plurality ofdifferent stimuli signals,

stimuli selector means coupled to said source of stimuli signals forautomatically selecting specific stimuli signals to be transferred tosaid equipment under test via said input/output terminals of saidinterface device,

switching means coupled between said selector means and said interfaceinput/output terminals for controlling the transfer of said stimulisignals from said selector means to said equipment under test,

a source of reference signals,

control means coupled to said stimuli selector means for producingcontrol signals, and

comparator means having first input terminals for receiving said signalsproduced by said equipment under test from said interface input/outputterminals, second input terminals coupled to said source of referencesignals and third input terminals coupled to said control means forcomparing signals from said equipment under test appearing at saidinterface input/output terminals to a reference signal selected inaccordance with said control signals thereby producing an output signalindicative of the result of said comparison,

2. An interface device as described in claim 1 in which said stimuliselector means includes register means coupled to said source of stimulisignals for storing selected stimuli signals.

3. An interface device as described in claim 2 which includes a delaymeans responsive to external gating and coupled to said register meansfor controlling the transfer of said selected stimuli signals stored insaid register means.

4. An interface device as described in claim 2 in which said registermeans includes a plurality of 8 bit shift registers coupled in parallel.

5. An interface device as described in claim 2 in which said stimuliselector means includes decoder means responsive to programmed datainput signals and coupled to said register means for providing outputselector signals.

6. An interface device as described in claim 5 in which said decodermeans includes an integrated circuit device that converts saidprogrammed data input signals in the form of a digital number intocorresponding output pulses on respective ones of a plurality of outputterminals.

7. An interface device as described in claim 1 in which said source ofstimuli signals includes means for simultaneously providing digitalones, zeroes, clock pulses and clock frequency signals.

8. An interface device as described in claim 1 in which said controlmeans includes delay means responsive to programmable bit input signals.

9. An interface device as described in claim 8 in which said delay meansincludes a plurality of 4 bit latch circuits.

a a a: a: a

1. An interface device for coupling between electronic test apparatusand equipment under test having a plurality of input/output terminals,each of said input/output terminals to be used as either an outputterminal for applying stimuli signals to the equipment under test or asan input terminal for receiving signals produced by said equipment undertest, said interface device comprising: a source of stimuli signals forsimultaneously providing a plurality of different stimuli signals,stimuli selector means coupled to said source of stimuli Signals forautomatically selecting specific stimuli signals to be transferred tosaid equipment under test via said input/output terminals of saidinterface device, switching means coupled between said selector meansand said interface input/output terminals for controlling the transferof said stimuli signals from said selector means to said equipment undertest, a source of reference signals, control means coupled to saidstimuli selector means for producing control signals, and comparatormeans having first input terminals for receiving said signals producedby said equipment under test from said interface input/output terminals,second input terminals coupled to said source of reference signals andthird input terminals coupled to said control means for comparingsignals from said equipment under test appearing at said interfaceinput/output terminals to a reference signal selected in accordance withsaid control signals thereby producing an output signal indicative ofthe result of said comparison.
 2. An interface device as described inclaim 1 in which said stimuli selector means includes register meanscoupled to said source of stimuli signals for storing selected stimulisignals.
 3. An interface device as described in claim 2 which includes adelay means responsive to external gating and coupled to said registermeans for controlling the transfer of said selected stimuli signalsstored in said register means.
 4. An interface device as described inclaim 2 in which said register means includes a plurality of 8 bit shiftregisters coupled in parallel.
 5. An interface device as described inclaim 2 in which said stimuli selector means includes decoder meansresponsive to programmed data input signals and coupled to said registermeans for providing output selector signals.
 6. An interface device asdescribed in claim 5 in which said decoder means includes an integratedcircuit device that converts said programmed data input signals in theform of a digital number into corresponding output pulses on respectiveones of a plurality of output terminals.
 7. An interface device asdescribed in claim 1 in which said source of stimuli signals includesmeans for simultaneously providing digital ones, zeroes, clock pulsesand clock frequency signals.
 8. An interface device as described inclaim 1 in which said control means includes delay means responsive toprogrammable bit input signals.
 9. An interface device as described inclaim 8 in which said delay means includes a plurality of 4 bit latchcircuits.